As semiconductor processes continue to scale downwards, e.g., shrink, the desired spacing between features (i.e., the pitch) also becomes smaller. To this end, in the smaller technology nodes it becomes ever more difficult to fabricate back end of line (BEOL) and middle of line (MOL) metallization features, e.g., interconnects, due to the critical dimension (CD) scaling and process capabilities, as well as materials that are used to fabricate such structures.
For example, to manufacture interconnect structures for source and drain contacts, it is necessary to remove dielectric material adjacent to the gate structures. The removal of the dielectric material is provided by an etching process which also tends to erode the spacer material of the gate structure. That is, the low-k dielectric material used for the spacer or sidewalls of the gate structure can be eroded away in the downstream etching processes used to form the openings for the drain and source contacts. This loss of material will expose the metal material of the gate structure, resulting in a short between the metal material of the gate structure and the metal material used to form the contact, itself.
Also, for smaller technology nodes, particularly those manufactured using non-self-aligned contact (SAC) schemes and extreme ultra violet (EUV) schemes, final gate height control between different macros is critical for device performance. However, the current chemical mechanical polishing (CMP) schemes, particularly for tungsten (W), is challenging to achieve the final gate height for the designed device performance. For example, macro-loading on different density macros is a fundamental issue for CMP multi-material polishing. More specifically, due to the macro loading issues in W gate CMP, in the long gate location, work function materials (WFM) become exposed which can result in source/drain to gate shorting issues.